1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although the dimension for each device is commonly reduced (refined) to increase memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, the costs of lithography process are ever increasing. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. That is, it is likely that difficulties would be encountered in device operation itself.
Therefore, such semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices.
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with a cylinder-type structure (see, for example, Japanese Patent Laid-Open No. 2007-266143). Those semiconductor storage devices using transistors with the cylinder-type structure are provided with multiple conductive layers corresponding to gate electrodes and pillar-like columnar semiconductors. Each columnar semiconductor serves as a channel (body) part of a respective transistor. Memory gate insulation layers are provided around the columnar semiconductors. Such a configuration including these conductive layers, columnar semiconductors, and memory gate insulation layers is referred to as a “memory string”.
In these conventional semiconductor storage devices with three-dimensional structures, those memory strings to be read at the same time have one ends connected to respective bit lines and the other ends connected to a common source line. This configuration has a problem that changes in the potential (potential floating) of the source line due to read current become larger and the read current becomes smaller as more memory cells are integrated and more memory strings are to be read at the same time, which results in a longer reading time. This configuration is also problematic in providing a sufficient read margin because the amount of potential floating of the source line varies depending on the position in the memory cell array, causing variations in read current.